The full performance of contemporary HPC systems can only be achieved if all levels of parallelism within the node are exploited: from multiple sockets and cores, over vector and acceleration units, to the memory hierarchy. In this talk, we will examine the corresponding research activities of RWTH's HPC group and the resulting extensions incorporated into standards and tools, such as OpenMP for example. We will also review closely related topics such as the tool-supported correctness analysis of parallel programs.

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