DELD Quiz

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DELD Quiz

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Decimal equivalent of a binary number 10010.011 is *

1 point

18.75

18.375

18.25

18.745

Binary equvqlent of decimal number 2048 is *

1 point

100000000000

011111111111

100000011101

111111111001

Octal equivalent of A3D.2F is *

1 point

5075.136

5075.036

5075.156

5075.25

Hexadecimal equivalent of a binary number 1011101.010111 is *

1 point

BA.5C

BA.17

5D.5C

5D.17

Binary equivalent of the gray code number 0111 0111 is *

1 point

0101 1010

0110 1101

1000 1000

None of these

The output of 3 input AND gate will be zero if *

1 point

All inputs are 0

At least 2 inputs are 0

At least one of the inputs is 0

All of these

Consider 4 input NOR gate with inputs A,B,C,D. What will happen of input D is permanently set to 0 *

1 point

The output will always 0

The output will always 1

It will behave like 3 input NOR gate with inputs A,B,C.

None of these

for 4 input Ex-OR Gate what will be the outputs for corresponding with the inputs 0011,1011 *

1 point

0 and 1

1 and 0

0 and 0

1 and 1

Number of select lines required to form 8:1 MUX from 2:1 are *

1 point

IC 74153 and I 74138 are *

1 point

MUX and DECODER ICs

ENCODER and DECODER ICs

ENCODER and DEMUX

MUX and DEMUX ICs

in Asynchronous counters LSB is Denoted by *

1 point

First FF connected in series

Last FF connected in series

None of these

The expression (A+B).(A+C).(A+D) is equivalent to *

1 point

A+(B.C.D)

A.B+B.C+C.D

CA+B.C+C.D+B.D

A.B.C.D

The duel of switching expression (x+(Y.0))+(z+1) is *

1 point

(X.(Y+1)).(Z.0)

(X.(Y+1)).(Z+0)

(X+(Y+1))+(Z.0)

(X+(Y+1)).(Z+0)

which of the following expressions are false? *

1 point

(A+B).C=(A+C).(B+C)

A+B.C=(A+B).(A+C)

A+A'B=A+B

A+A'B=A+B'

Required

The minimized form of the switching expression F=X'Y'+X'Z+Y'Z+X.Y is *

1 point

X'Y'+XY+Z

X'Y'+YZ

X'Z+XY

XY+YZ

The expression (A.B+A'.B+B.C)' in SOP form is *

1 point

A'B'+AB+B'C

A'B'+BC'

None of these

for 3 input Ex-OR function of variables A,B,C set of all minterms are *

1 point

A'B'C',ABC

AB'C',A'BC',A'B'C,ABC

A'B'C',ABC,A'B'C,AB'C

We can design a full subtractor by using design of a full adder *

1 point

TRUE

FALSE

-----------counters are prone to delay *

1 point

Synchronous counters

Asynchronous counters

Option 3

-----FFs are generally used to store data in Buffer Registers

1 point

T-FF

J-K FF

D-FF

S-R FF

Clear selection

Number of states in Johnson's counter are *

1 point

2 * No. of Flip Flops used

No. of Flip Flops used

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