Jeff Nigh, Intel Corporation
Thursday, March 19, 2020 at 10:00 AM-4:30 PM
120 Lewis Science Library, Princeton University

This is workshop is open to all members of the PU community. Lunch will be provided to RSVPs.


---- Workshop Schedule ----

10:00 AM-12:00 PM   Introduction to Field-Programmable Gate Arrays (FPGAs)

12:00 PM-1:00 PM   Lunch

The afternoon session will focus on specialized training. For those just looking for an overview of FPGAs, the morning session should be sufficient.

1:00 PM-2:00 PM   Session 1
    -- OneAPI for FPGA flow
    -- Data Parallel C++ (DPC++) / SYCL
    -- https://software.intel.com/en-us/oneapi/fpga

2:15 PM-3:15 PM   Session2
    -- OpenCL for FPGA flow
    -- https://www.intel.com/content/www/us/en/software/programmable/sdk-for-opencl/overview.html
 
3:30-4:30 PM   Session 3
    -- High Level Synthesis (HLS) C++ for FPGA flow
    -- https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html

Instructor Bio: Jeff has been involved with Programmable Logic for over 30 years starting in Avionics design for Rockwell Collins working on FPGAs for cockpit displays and for the last 19 years with Intel in the Intel Programmable Solutions Group (FPGA) in Field Applications Engineering, technical account management and most recently as a Technical Solutions Specialist for the FPGA acceleration products.


---- FPGAs at Princeton ----

Research Computing recently installed four Intel FPGAs on the Della cluster. After attending this workshop you should have the skills needed to start using these devices. If you have an account on Della then use this command to connect: ssh YourNetID@della-fpga1.princeton.edu. The node della-fpga2.princeton.edu is also available. Each node has 2 FPGAs. For all questions about the FPGAs on Della please write to cses@princeton.edu.


---- About FPGAs ----

While the Field Programmable Gate Array (FPGA) is very flexible, it historically required deep FPGA expertise and special programming skills in RTL (VHDL/Verilog). In the recent years Intel has spent time, energy and dollars to bring FPGAs to the masses by supporting higher level languages like C++, OpenCL, and most recently Data Parallel C++ (OneAPI)  https://software.intel.com/en-us/oneapi.
 
The FPGA is not meant to be a GPU replacement nor a CPU replacement, but another tool in the heterogenous compute tool belt that can help augment performance.
 
One area where the FPGA is well suited for is, inline acceleration where the FPGA can Ingest data directly off an ethernet interface, process in real time and then pass the information up to the host for further processing:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01278-fpga-inline-acceleration-for-streaming-analytics.pdf
 
Another area is with AI video inference with OpenVINO, with the ability to encrypt the weights along with streaming AI video analytics and database acceleration.
https://www.youtube.com/watch?v=1GfZpubYm8s
https://www.intel.com/content/www/us/en/programmable/solutions/acceleration-hub/solutions.html
 
Here is an example of how the University of Tsukuba created a cluster utilizing, CPU, GPU and FPGA where the FPGA is utilized for the ARGOT ray tracing portion of research.
https://www.youtube.com/watch?v=Vrlq5Q-3f0o
 
There are vast array of other use cases, and now with C++, OpenCL, and Data Parallel C++ software engineers and researchers can now harness the power of the FPGA.