The Big Chiplet Survey (2024)

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Composable chiplets have the potential of revolutionaizing the $1T global electronics market, but only if we build the right set of chiplets. This is your chance to help drive the chiplet community in the right direction to make sure your needs are served! Individual answers will be kept private, but a summary of the results will be shared with all participants!

Email *

Name

Affiliation

End application domain

R&D

AI training (datacenter)

AI inference (datacenter)

Automotive

Aerospace & Defense

Wireline Communication (Networking)

Manufacturing

Wireless Communication

Consumer Electronics

Robotics

Supercomputing

Test and Measurement

Space

Health

Education

IoT

Other:

Clear selection

What is your specifific application? (optional)

What are your top 3 issues with existing commercial SoCs?

Missing features

Performance

Cost

Size

Power

Operating range (temp, radiation, etc)

Security

Access

Lock-in

Software

NDAs

Other:

What is the main reason for not designing your own chips?

No need

High cost

Development time

Risk

Lack of expertise

Other:

Clear selection

System processing requirements

RISC-V CPU

ARM CPU

GPU

FPGA

NPU/TPU

VPU (Vector Processor)

ISP (Image Signal Processor)

DSP

Video Accelerator

Crypto Accelerator

Other:

System IO requirements

GPIO

UART, SPI, I2C, JTAG, ...

Ethernet

PCIE

USB

MIPI

HDMI

DisplayPort

SERDES

LVDS

High Speed ADC (>10MSPS)

High Speed DAC (>10MSPS)

Other:

System Memory Requirements

LPDDR

DDR

GDDR

HBM

NVM

Global Cache Coherency

Other:

Analog Requirements

Power management

System monitors (process, voltage, temp, stress)

Clock generation

Amplifiers

Filters

Other:

Operating System

Not applicable

Linux

Andoird

Bare metal

RTOS

Other:

Preferred Device Packaging

Bare die (chiplet, known good die)

Package (SiP, MCM, BGA,...)

System-On-Module (SOM)

Board (PCIe, SBC, motherboard)

Other:

Clear selection

Preferred Chiplet IO Standard *

BoW

UCIe (Advanced)

UCIe (Standard)

Don't know

AIB

Other:

Preferred Chiplet Communication Protocol *

CXL

Don't know

AXI

CHI C2C

UMI (https://github.com/zeroasiccorp/umi)

PCIe

Other:

Current Design Cycle (months)

< 1

< 3

< 6

< 9

< 12

< 18

< 36

> 36

Clear selection

Total Performance

< 1 GOPS

< 10 GOPS

< 100 GOPS

< 1 TOPS

< 10 TOPS

< 100 TOPS

< 1,000 TOPS

> 1,000 TOPS

Clear selection

Total Memory Bandwidth

< 1 GB/s

< 10 GB/s

< 100 GB/s

< 1,000 GB/s

> 1,000 GB/s

Clear selection

Total Memory Capacity

< 100 MB

< 1 GB

< 10 GB

< 100 GB

< 1,000 GB

> 1,000 GB

Clear selection

Total On-Chip Memory

< 1 MB

< 10 MB

< 100 MB

< 1000 MB

> 1,000 MB

Clear selection

Total IO Bandwidth

< 1 Gbps

< 10 Gbps

< 100 Gbps

< 1,000 Gbps

> 1,000 Gbps

Clear selection

Total FPGA LUTs

<1,000

<10,000

<100,000

<1,000,000

>1,000,000

Clear selection

Total IO Signals

< 10

< 100

< 1,000

> 1,000

Clear selection

Total Chip Power

< 100 mW

< 1 W

< 10 W

< 100 W

> 100W

Clear selection

Maximum Device Size (mm x mm)

< 1 x 1

< 3 x 3

< 10 x 10

< 20 x 20

< 30 x 30

< 40 x 40

< 100 x 100

> 100 x 100

Clear selection

Total Devices Needed

< 10

< 100

< 1,000

< 10,000

< 100,000

< 1,000,000

> 1,000,000

> 10,000,000

Other:

Clear selection

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