RISC-V,
an open standard Instruction Set Architecture (ISA) enabling a new era of processor innovation through open collaboration, supports professors and students through events, trainings, lecture resources and mentorships. In order to make universities aware of new and existing resources we would like to know what you teach and who to contact at your university with new resources.
If your university is not a member, did you know you can join for free?
https://riscv.org/membership/Once you join as a member you can participate in the Academic and Training Special Interest Group:
https://lists.riscv.org/g/sig-academia-trainingQuestions? Email
learn@riscv.org