We are planning for following FREE Webinar Sessions on:
1. Partial Reconfiguration with FPGA: Creating x4R crypto project with Partial Reconfiguration Model
2. Machine Learning with Xilinx-Vitis-AI and MPSoC FPGA
3. Designing Machine Learning Processor in RTL(VHDL/Verilog) + HLS
4. PCIe based Development with FPGA: Developing with UltraScale and UltraScale+ FPGA from Xilinx
If you are interested on it, then please fill the following google form. We will also mail you the schedule of the webinar before one week it going to hosted. The Recorded Links will be shared with the registered enthusiast.
For more details about LogicTronix, please visit:
www.LogicTronix.com/webinars/In February and March, 2019 we hosted "Webinar Series on FPGA-Part I" on following topics:
1. Hardware Design Debugging with Xilinx VIVADO Tool: Using ILA, VIO, Setup Debug Options on Hardware Debugging
2. Writing Complex VHDL/Verilog Design Systems: An example of AES Encryption/Decryption Design
3. Development of Computer Vision System and Machine Learning Applications with Xilinx Zynq FPGA and HLS/SDSoC.
4. Design with SDAccel, Alveo and VCU1525 Cards: Overview of tools and FPGA's, basic application development with SDAccel for VCU 1525 and Alveo.
If you want to watch the recorded version of above Webinar Series-Part I, then please visit:
www.LogicTronix.com/webinars/